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a
Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming AD808
frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition. The AD808 acquires frequency and phase lock on input data using two control loops that work without requiring external control. The frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. At frequency lock, the frequency error is zero and the frequency detector has no further effect. The phase acquisition control loop then works to ensure that the output phase tracks the input phase. A patented phase detector has virtually eliminated pattern jitter throughout the AD808. The device VCO uses a ring oscillator architecture and patented low noise design techniques. Jitter is 2.5 degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the IC. The device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance. The user sets the jitter peaking and acquisition time of the PLL by choosing a damping factor capacitor whose value determines loop damping. CCITT G.958 Type A jitter transfer requirements can easily be met with a damping factor of 5 or greater. Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, CD, brings the clock output frequency to the VCO center frequency. The AD808 consumes 400 mW and operates from a single power supply at either +5 V or -5.2 V.
FEATURES Meets CCITT G.958 Requirements for STM-4 Regenerator--Type A Meets Bellcore TR-NWT-000253 Requirements for OC-12 Output Jitter: 2.5 Degrees RMS 622 Mbps Clock Recovery and Data Retiming Accepts NRZ Data, No Preamble Required Phase-Locked Loop Type Clock Recovery-- No Crystal Required Quantizer Sensitivity: 4 mV Level Detect Range: 10 mV to 40 mV, Programmable Single Supply Operation: +5 V or -5.2 V Low Power: 400 mW 10 KH ECL/PECL Compatible Output Package: 16-Lead Narrow 150 mil SOIC
PRODUCT DESCRIPTION
The AD808 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 622 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-12 or SDH STM-4 fiber optic receiver. The receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at the signal level detect output. The PLL has a factory trimmed VCO center frequency and a frequency acquisition control loop that combine to guarantee
FUNCTIONAL BLOCK DIAGRAM
CF1 PIN NIN QUANTIZER
DET
CF2
COMPENSATING ZERO PHASE-LOCKED LOOP
LOOP FILTER
VCO THRADJ SIGNAL LEVEL DETECTOR LEVEL DETECT COMPARATOR/ BUFFER FDET RETIMING DEVICE CLKOUTP CLKOUTN DATAOUTP DATAOUTN
AD808
SDOUT
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
AD808-SPECIFICATIONS (T = T
A
MIN to TMAX , VS
= VMIN to VMAX, CD = 0.47 F, unless otherwise noted)
Min 2.5 10 5 Typ Max VS 4.0 2.0 1.0 10 100 1.5 800 10 2 50 10 18 40 5 5.1 7.0 4.7 0.2 622.08 620 620 624 624 81 900 1050 50 3.6 3.6 13.5 23 45.5 1.5 9.0 9.0 10.0 0.4 Units V mV mV mV A V mV MHz k pF ps mV mV mV s dB dB dB V V MHz MHz MHz Degrees ps ps Degrees Degrees rms Degrees rms Unit Intervals Unit Intervals Unit Intervals Unit Intervals Unit Intervals dB kHz
Parameter QUANTIZER-DC CHARACTERISTICS Input Voltage Range Input Sensitivity, VSENSE Input Overdrive, VOD Input Offset Voltage Input Current Input RMS Noise Input Peak-to-Peak Noise QUANTIZER-AC CHARACTERISTICS Upper -3 dB Bandwidth Input Resistance Input Capacitance Pulsewidth Distortion LEVEL DETECT Level Detect Range
Condition @ PIN or N IN PIN-NIN, Figure 1, BER = 1 x 10 -10 Figure 1, BER = 1 x 10 -10 BER = 1 x 10-10 BER = 1 x 10-10
600
Response Time Hysteresis (Electrical)
SDOUT Output Logic High SDOUT Output Logic Low PHASE-LOCKED LOOP NOMINAL CENTER FREQUENCY CAPTURE RANGE TRACKING RANGE STATIC PHASE ERROR (See Figure 7) SETUP TIME (tSU) HOLD TIME (t H) PHASE DRIFT JITTER JITTER TOLERANCE
RTHRESH = 22.1 k RTHRESH = 6.98 k RTHRESH = 0 DC Coupled RTHRESH = 22.1 k (See Figure 8) RTHRESH = 6.98 k RTHRESH = 0 Load = +3.2 mA Load = -3.2 mA
6.5 13 28.5 0.1 3.0 3.0 4.0
27 -1 PRN Sequence Figure 2 Figure 2 240 Bits, No Transitions 27 -1 PRN Sequence 223 -1 PRN Sequence f = 30 Hz f = 300 Hz f = 25 kHz f = 250 kHz f = 5 MHz CD = 0.47 F 223 -1 PRN Sequence, TA = +25C VCC = 5 V, VEE = GND VMIN to V MAX VCC = 5.0 V, VEE = GND, TA = +25C TA = +25C Referenced to VCC = 1/2, TA = +25C, VCC = 5 V, VEE = GND 20%-80% 80%-20% Positive Number Indicates Clock Leading Data
22 550 700 2.5 2.5 3000 300 3.7 0.56 0.45 0.04 333 2 x 106 8 x 106 4.5 55 -1.2 -2.2 45 174 136 -100 350 315 130 80 -1.0 -2.0
24 1.7 0.28 0.18
JITTER TRANSFER Peaking (Figure 14) Bandwidth Acquisition Time C D = 0.1 F C D = 0.47 F POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT PECL OUTPUT VOLTAGE LEVELS Output Logic High, V OH Output Logic Low, V OL SYMMETRY (Duty Cycle) Recovered Clock Output, Pin 5 OUTPUT RISE / FALL TIMES Rise Time (t R) Fall Time (t F) CLOCK SKEW (tRCS)
Specifications subject to change without notice.
450
3 x 106 Bit Periods 12 x 106 Bit Periods 5.5 Volts 100 -0.7 -1.7 55 500 500 250 mA Volts Volts % ps ps ps
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AD808
ABSOLUTE MAXIMUM RATINGS 1 PIN FUNCTION DESCRIPTIONS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8 V Input Voltage (Pin 12 or Pin 13) . . . . . . . . . . . . . . VCC + 0.6 V Maximum Junction Temperature . . . . . . . . . . . . . . . . +165C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . 1500 V
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics: 16-Lead Narrow Body SOIC Package: JA = 110C/Watt.
OUTPUT NOISE 1
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12
Mnemonic DATAOUTN DATAOUTP VCC2 CLKOUTN CLKOUTP VCC1 CF1 CF2 AV EE THRADJ AVCC1 NIN PIN AVCC2 SDOUT VEE
Description Differential Retimed Data Output Differential Retimed Data Output Digital VCC for ECL Outputs Differential Recovered Clock Output Differential Recovered Clock Output Digital VCC for Internal Logic Loop Damping Capacitor Loop Damping Capacitor Analog VEE Level Detect Threshold Adjust Analog VCC for PLL Quantizer Differential Input Quantizer Differential Input Analog VCC for Quantizer Signal Detect Output Digital VEE for Internal Logic
PIN CONFIGURATION
0 INPUT (V) OFFSET OVERDRIVE SENSITIVITY
13 14 15 16
Figure 1. Input Sensitivity, Input Overdrive
DATAOUT 50% (PIN 2) HOLD TIME CLKOUT 50% (PIN 5)
DATAOUTN 1 DATAOUTP 2 VCC2 3 CLKOUTN 4
16 15 14
VEE SDOUT AVCC2
tH
SETUP TIME
tSU tRCS
RECOVERED CLOCK SKEW
Figure 2. Setup and Hold Time
PIN TOP VIEW CLKOUTP 5 12 NIN (Not to Scale) VCC1 6 11 AVCC1
13
AD808
CF1 7 CF2 8
10 9
THRADJ AVEE
ORDERING GUIDE
Model AD808-622BR AD808-622BRRL7 AD808-622BRRL
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 16-Pin Narrowbody SOIC 750 Pieces, 7" Reel 2500 Pieces, 13" Reel
Package Option R-16A R-16A R-16A
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD808 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD808
DEFINITION OF TERMS Maximum, Minimum and Typical Specifications Tracking Range
Specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. Typical specifications are the mean of the distribution of the data for that parameter. If a parameter has a maximum (or a minimum), that value is calculated by adding to (or subtracting from) the mean six times the standard deviation of the distribution. This procedure is intended to tolerate production variations: if the mean shifts by 1.5 standard deviations, the remaining 4.5 standard deviations still provide a failure rate of only 3.4 parts per million. For all tested parameters, the test limits are guardbanded to account for tester variation to thus guarantee that no device is shipped outside of data sheet specifications.
Input Sensitivity and Input Overdrive
This is the range of input data rates over which the AD808 will remain in lock.
Capture Range
This is the range of input data rates over which the AD808 will acquire lock.
Static Phase Error
This is the steady-state phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling instant, which is assumed to be halfway between the rising and falling edges of a data bit. Gate delays between the signals that define static phase error, and IC input and output signals prohibit direct measurement of static phase error.
Data Transition Density,
Sensitivity and Overdrive specifications for the Quantizer involve offset voltage, gain and noise. The relationship between the logic output of the quantizer and the analog voltage input is shown in Figure 1. For sufficiently large positive input voltage the output is always Logic 1 and similarly, for negative inputs, the output is always Logic 0. However, the transitions between output Logic Levels 1 and 0 are not at precisely defined input voltage levels, but occur over a range of input voltages. Within this Zone of Confusion, the output may be either 1 or 0, or it may even fail to attain a valid logic state. The width of this zone is determined by the input voltage noise of the quantizer (1.5 mV at the 1 x 10-10 confidence level). The center of the Zone of Confusion is the quantizer input offset voltage (1 mV typ). Input Overdrive is the magnitude of signal required to guarantee correct logic level with 1 x 10-10 confidence level. With a single-ended PIN-TIA (Figure 3), ac coupling is used and the inputs to the Quantizer are dc biased at some commonmode potential. Observing the Quantizer input with an oscilloscope probe at the point indicated shows a binary signal with average value equal to the common-mode potential and instantaneous values both above and below the average value. It is convenient to measure the peak-to-peak amplitude of this signal and call the minimum required value the Quantizer Sensitivity. Referring to Figure 1, since both positive and negative offsets need to be accommodated, the Sensitivity is twice the Overdrive. The AD808 Quantizer has 4 mV Sensitivity typical. With a differential TIA (Figure 3), Sensitivity seems to improve from observing the Quantizer input with an oscilloscope probe. This is an illusion caused by the use of a single-ended probe. A 2 mV peak-to-peak signal appears to drive the AD808 Quantizer. However, the single-ended probe measures only half the signal. The true Quantizer input signal is twice this value since the other Quantizer input is a complementary signal to the signal being observed.
Response Time
This is a measure of the number of data transitions, from "0" to "1" and from "1" to "0," over many clock periods. is the ratio (0 1) of data transitions to bit periods.
Jitter
This is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms or Unit Intervals (UI). Jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. Jitter on the recovered clock causes jitter on the retimed data.
Output Jitter
This is the jitter on the retimed data, in degrees rms, due to a specific pattern or some pseudorandom input data sequence (PRN Sequence).
Jitter Tolerance
Jitter Tolerance is a measure of the AD808's ability to track a jittery input data signal. Jitter on the input data is best thought of as phase modulation, and is usually specified in unit intervals. The PLL must provide a clock signal that tracks the phase modulation in order to accurately retime jittered data. In order for the VCO output to have a phase modulation that tracks the input jitter, some modulation signal must be generated at the output of the phase detector. The modulation output from the phase detector can only be produced by a phase error between its data input and its clock input. Hence, the PLL can never perfectly track jittered data. However, the magnitude of the phase error depends on the gain around the loop. At low frequencies, the integrator of the AD808 PLL provides very high gain, and thus very large jitter can be tracked with small phase errors between input data and recovered clock. At frequencies closer to the loop bandwidth, the gain of the integrator is much smaller, and thus less input jitter can be tolerated. The AD808 output will have a bit error rate less than 1 x 10-10 when in lock and retiming input data that has the CCITT G.958 specified jitter applied to it.
Jitter Transfer (Refer to Figure 14)
Response time is the delay between removal of the input signal and indication of Loss of Signal (LOS) at SDOUT. The response time of the AD808 (1.5 s maximum) is much faster than the SONET/SDH requirement (3 s response time 100 s). In practice, the time constant of the ac coupling at the Quantizer input determines the LOS response time.
Nominal Center Frequency
The AD808 exhibits a low-pass filter response to jitter applied to its input data.
Bandwidth
This describes the frequency at which the AD808 attenuates sinusoidal input jitter by 3 dB.
Peaking
This describes the maximum jitter gain of the AD808 in dB.
This is the frequency at which the VCO will oscillate with the loop damping capacitor, CD, shorted. -4- REV. 0
AD808
Damping Factor,
Damping factor, describes the compensation of the second order PLL. A larger value of corresponds to more damping and less peaking in the jitter transfer function.
Acquisition Time
is useful to bypass the common mode of the preamp to the positive supply as well, if this is an option. Note, it is not necessary to use capacitive coupling of the input signal with the AD808. Figure 14 shows the input common-mode voltage can be externally set.
AVCC 500 PIN 5k 5k NIN AVEE OUT 500
This is the transient time, measured in bit periods, required for the AD808 to lock onto input data from its free-running state. Symmetry is calculated as (100 x on time)/period, where on time equals the time that the clock signal is greater than the midpoint between its "0" level and its "1" level.
Symmetry--Recovered Clock Duty Cycle
VCM
4mVp-p
a. Quantizer Differential Input Stage
SCOPE PROBE INPUT
AD808 QUANTIZER
BINARY OUTPUT 1.2V +VBE 6k THRADJ 80k
VCM
AVEE
b. Threshold Adjust a. Single-Ended Input Application
VCC1 VCM 2mVp-p IOH SCOPE PROBE +INPUT -INPUT BINARY OUTPUT VEE VCM 30
AD808 QUANTIZER
30 IOL
SDOUT
c. Signal Detect Output (SDOUT)
VCC2 140 140
b. Differential Input Application Figure 3. (a-b) Single-Ended and Differential Input Applications
DIFFERENTIAL OUTPUT
The AD808 has internal circuits to set the common-mode voltage at the quantizer inputs PIN (Pin 13) and NIN (Pin 12) as shown in Figure 4a. This allows very simple capacitive coupling of the signal from the preamp in the AD808 as shown in Figure 3. The internal common-mode potential is a diode drop (approximately 0.8 V) below the positive supply as shown in Figure 4a. Since the common mode is referred to the positive supply, it
7.8mA VEE
d. PLL Differential Output Stage--DATAOUT(N), CLKOUT(N) Figure 4. (a-d) Simplified Schematics
REV. 0
-5-
AD808-Typical Performance Characteristics
90000 80000 70000 60000 RTHRESH - SAMPLES 50000 40000 30000 20000 10000 0 4 180 160 140 120 100 80 60 40 20 0 6 8 10 12 SIGNAL DETECT VOLTAGE - mV 14 16 2.00 2.67 3.33 4.00 4.67 5.33 LOS HYSTERESIS - dB 6.00 6.67
Figure 5. Signal Detect Voltage vs. RTHRESH
Figure 8. Histogram LOS Hysteresis 22.1 k RTHRESH (All Temperature All Supply)
8.0 7.5 ELECTRICAL HYSTERESIS - dB 7.0 6.5 RTH = 5k 6.0 5.5 5.0 4.5 4.0 -40 RTH = 7k SAMPLES RTH = 0
200 180 160 140 120 100 80 60 40 20 -20 0 20 40 60 80 95 0 1.44 1.80 2.16 2.52 2.88 3.24 JITTER - Degrees 3.60 3.96 TEST CONDITIONS WORST CASE: -40 C
TEMPERATURE - C
Figure 6. Signal Detect Hysteresis vs. Temperature
Figure 9. Output Jitter Histogram
12
100 25 C 85 C JITTER TOLERANCE - UI
10
8 SAMPLES
10
-40 C
6
SONET MASK 1
4
2
0 0 8 17 25 33 42 STATIC PHASE - Degrees 50 58
0.1 1
10
100 1k 10k 100k JITTER FREQUENCY - Hz
1M
10M
Figure 7. Histogram of Static Phase -40 @ 4.4 V
Figure 10. Jitter Tolerance vs. Frequency
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AD808
THEORY OF OPERATION Quantizer
DATA INPUT
DET
S+1
1 S
The quantizer (comparator) has three gain stages, providing a net gain of 350. The quantizer takes full advantage of the Extra Fast Complementary Bipolar (XFCB) process. The input stage uses a folded cascode architecture to virtually eliminate pulse width distortion, and to handle input signals with commonmode voltage as high as the positive supply. The input offset voltage is factory trimmed and is typically less than 1 mV. XFCB's dielectric isolation allows the different blocks within this mixedsignal IC to be isolated from each other, hence the 4 mV Sensitivity is achieved. Traditionally, high speed comparators are plagued by crosstalk between outputs and inputs, often resulting in oscillations when the input signal approaches 10 mV. The AD808 quantizer toggles at 2 mV (4.0 mV sensitivity) at the input without making bit errors. When the input signal is lowered below 2 mV, circuit performance is dominated by input noise, and not crosstalk.
Signal Detect
VCO FDET RETIMING DEVICE RECOVERED CLOCK OUTPUT RETIMED DATA OUTPUT
Figure 12. PLL Block Diagram
The input to the signal detect circuit is taken from the first stage of the quantizer. The input signal is first processed through a gain stage. The output from the gain stage is fed to both a positive and a negative peak detector. The threshold value is subtracted from the positive peak signal and added to the negative peak signal. The positive and negative peak signals are then compared. If the positive peak, POS, is more positive than the negative peak, NEG, the signal amplitude is greater than the threshold, and the output, SDOUT, will indicate the presence of signal by remaining low. When POS becomes more negative than NEG, the signal amplitude has fallen below the threshold, and SDOUT will indicate a loss of signal (LOS) by going high. The circuit provides hysteresis by adjusting the threshold level higher by a factor of two when the low signal level is detected. This means that the input data amplitude needs to reach twice the set LOS threshold before SDOUT will signal that the data is again valid. This corresponds to a 3 dB optical hysteresis.
THRESHOLD AD808 BIAS COMPARATOR STAGES + & CLOCK RECOVERY PLL + ITHR
The frequency detector delivers pulses of current to the charge pump to either raise or lower the frequency of the VCO. During the frequency acquisition process the frequency detector output is a series of pulses of width equal to the period of the VCO. These pulses occur on the cycle slips between the data frequency and the VCO frequency. With a maximum density data pattern (1010 . . . ), every cycle slip will produce a pulse at the frequency detector output. However, with random data, not every cycle slip produces a pulse. The density of pulses at the frequency detector output increases with the density of data transitions. The probability that a cycle slip will produce a pulse increases as the frequency error approaches zero. After the frequency error has been reduced to zero, the frequency detector output will have no further pulses. At this point the PLL begins the process of phase acquisition, with a settling time of roughly 2000 bit periods. Jitter caused by variations of density of data transitions (pattern jitter) is virtually eliminated by use of a new phase detector (patented). Briefly, the measurement of zero phase error does not cause the VCO phase to increase to above the average run rate set by the data frequency. The jitter created by a 27-1 pseudorandom code is 1/2 degree, and this is small compared to random jitter. The jitter bandwidth for the PLL is 0.06% of the center frequency. This figure is chosen so that sinusoidal input jitter at 350 Hz will be attenuated by 3 dB. The damping ratio of the PLL is user programmable with a single external capacitor. At 622 MHz, a damping ratio of 5 is obtained with a 0.47 F capacitor. More generally, the damping ratio scales as (fDATA x CD)1/2. A lower damping ratio allows a faster frequency acquisition; generally the acquisition time scales directly with the capacitor value. However, at damping ratios approaching one, the acquisition time no longer scales directly with capacitor value. The acquisition time has two components: frequency acquisition and phase acquisition. The frequency acquisition always scales with capacitance, but the phase acquisition is set by the loop bandwidth of the PLL and is independent of the damping ratio. In practice the acquisition time is dominated by the frequency acquisition. The fractional loop bandwidth of 0.06% should give an acquisition time of 2000 bit periods. However, the actual acquisition time is several million bit periods and is comprised mostly of the time needed to slew the voltage on the damping capacitor to final value.
PIN NIN
IHYS
POSITIVE PEAK DETECTOR NEGATIVE PEAK DETECTOR
LEVEL SHIFT DOWN LEVEL SHIFT UP
SDOUT
Figure 11. Signal Level Detect Circuit Block Diagram
Phase-Locked Loop
The phase-locked loop recovers clock and retimes data from NRZ data. The architecture uses a frequency detector to aid initial frequency acquisition; refer to Figure 12 for a block diagram. Note the frequency detector is always in the circuit. When the PLL is locked, the frequency error is zero and the frequency detector has no further effect. Since the frequency detector is always in the circuit, no control functions are needed to initiate acquisition or change mode after acquisition.
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AD808
Center Frequency Clamp (Figure 13)
An N-channel FET circuit can be used to bring the AD808 VCO center frequency to within 10% of 622 MHz when SDOUT indicates a Loss of Signal (LOS). This effectively reduces the frequency acquisition time by reducing the frequency error between the VCO frequency and the input data frequency at clamp release. The N-FET can have "on" resistance as high as 1 k and still attain effective clamping. However, the chosen N-FET should have greater than 10 M "off" resistance and less than 100 nA leakage current (source and drain) so as not to alter normal PLL performance.
1 DATAOUTN 2 DATAOUTP 3 VCC2 4 CLKOUTN 5 CLKOUTP 6 VCC1 N_FET CD 7 CF1 8 CF2 VEE 16 SDOUT 15 AVCC2 14 PIN 13 NIN 12 AVCC1 11 THRADJ 10
CD 0.047 0.10 0.47
PEAK 0.11 0.07 0.04
DIV 20.00m RBW:
DIV START 36.00m STOP 30Hz ST: 3.07 min RANGE: R=
500.000Hz 100 000.000Hz 0, T= 0dBm
Figure14. Jitter Transfer vs. CD
AD808
AVEE
9
Figure 13. Center Frequency Clamp Schematic
C1 0.1 F R1 R2 100 100 J1 C3 0.1 F DATAOUTN DATAOUTP J2 C4 0.1 F J3 C5 0.1 F CLKOUTN CLKOUTP J4 C6 0.1 F R4 R3 100 100 R7 100 R8 100 C7 R9 154 R5 100 R6 100 R10 154 50 STRIP LINE EQUAL LENGTH 1 DATAOUTN 2 DATAOUTP 3 VCC2 4 CLKOUTN 5 CLKOUTP C8 TP1 R11 154 R12 CD 154 TP2 6V CC1 7 CF1 8 CF2 VEE 16 R13 301 C9 R16 3.65k R15 C13 0.1 F J6 49.9 PIN NIN C14 0.1 F J7 C10 TP5 RTHRESH TP6
VECTOR PINS SPACED FOR RN55C TYPE RESISTOR; COMPONENT SHOWN FOR REFERENCE ONLY
TP7 TP8
J5 SDOUT C12 0.1 F
SDOUT 15 AVCC2 14 PIN 13 NIN 12 AVCC1 11 THRADJ 10
R14 49.9
C2 0.1 F
AD808
AVEE
9
NOTE: C7-C10 ARE 0.1F BYPASS CAPACITORS RIGHT ANGLE SMA CONNECTOR OUTER SHELL TO GND PLANE ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT TPxo TEST POINTS ARE VECTORBOARD K24A/M PINS
NOTE: INTERCONNECT RUN UNDER DUT VECTOR PINS SPACED THROUGH-HOLE CAPACITOR ON VECTOR CUPS; COMPONENT SHOWN FOR REFERENCE ONLY
C11 TP3 10 F TP4 +5V GND
Figure 15. Evaluation Board Schematic
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AD808
USING THE AD808 Acquisition Time Loop Damping Capacitor, C D
This is the transient time, measured in bit periods, that required for the AD808 to lock onto the input data from its free running state.
Ground Planes
A ceramic capacitor may be used for the loop damping capacitor. Using a 0.47 F, 20% capacitor provides < 0.1 dB jitter peaking.
AD808 Output Squelch Circuit
The use of one ground plane for connections to both analog and digital grounds is recommended. The use of a 10 F capacitor between VCC and ground is recommended. The +5 V power supply connection to VCC2 should be carefully isolated. The VCC2 pin is used inside the AD808 to provide the CLKOUT and DATAOUT signals. Use a 0.1 F decoupling capacitor between IC power supply input and ground. This decoupling capacitor should be positioned as closed to the IC as possible. Refer to the schematic in Figure 15 for advised connections.
Transmission Lines Power Supply Connections
A simple P-channel FET circuit can be used in series with the Output Signal ECL Supply (VCC2, Pin 3) to squelch clock and data outputs when SDOUT indicates a loss of signal (Figure 16). The VCC2 supply pin draws roughly 72 mA (14 mA for each of 4 ECL loads, plus 16 mA for all 4 ECL output stages). This means that selection of a FET with ON RESISTANCE of 0.5 will affect the common mode of the ECL outputs by only 36 mV.
5V TO VCC1, AVCC, AVCC2 P_FET
1 DATAOUTN 2 DATAOUTP 3 VCC2 BYPASS CAP 4 CLKOUTN 5 CLKOUTP 6 VCC1 7 CF1 8 CF2
VEE 16 SDOUT 15 AVCC2 14 PIN 13 NIN 12 AVCC1 11 THRADJ 10
Use 50 transmission line for PIN, NIN, CLKOUT, and DATAOUT signals.
Terminations
Use metal, thick-film, 1% termination resistors for PIN, NIN, CLKOUT, and DATAOUT signals. These termination resistors must be positioned as close to the IC as possible. Use individual connections, not daisy chained, for connections from the +5 V to load resistors for PIN, NIN, CLKOUT, and DATAOUT signals.
AD808
AVEE
9
Figure 16. Squelch Circuit Schematic
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AD808
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead Small Outline IC Package (R-16A)
0.3937 (10.00) 0.3859 (9.80)
16 1 9 8
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
0.0500 SEATING (1.27) PLANE BSC
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
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C3262-8-1/98
PRINTED IN U.S.A.

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